1. Field of the Invention
The present invention relates generally to a computer implemented method, and computer program product for detecting faults or out-of-tolerance performance in circuits at nanometer scales. More specifically, the present invention relates to determining leakage current, drive current, and thus effective gate length and carrier mobility for a design of a physical circuit.
2. Description of the Related Art
Moore's law is a paradigm of competitiveness that states that semiconductor manufacturers must attain circuit density improvements on an order of 100% improvement over 12 to 18 month timescales. Such design goals result in circuit designers building integrated circuits with smaller tolerances with each stage of technology evolution. For example, current design technologies that apply 65 nm complementary metal oxide semiconductors (CMOS) now must account for mechanical stress as a factor that affects the quantum movements of electrons in a circuit. Stress inducing materials such as SiGe, nitride liners, and shallow trench isolation (STI) can vary stress across the width of transistor geometry. In particular, the generally rectangular cross-section of a gate and channel can have a stress profile that varies as a function of displacement from a gate input or other threshold, but not necessarily only because of the displacement from gate input.
As a result, compressive or tensile forces at each slice of a gate can either contribute to, or diminish electron or hole mobility through the gate. These changes, if not accounted for can cause the threshold voltage, Vth, carrier mobility or both to change beyond design tolerances. Accordingly, previous generations of circuit designers have proceeded with a design by assuming the electron mobility remained constant through each profile of a MOS gate. A metal oxide semiconductor (MOS) gate is a voltage-controlled switch that conducts when a gate-to-source voltage is above a threshold voltage. The MOS gate is constructed from silicon doped with a dopant to form a source and a drain. The MOS gate includes a gate that is disposed in a manner to form a channel of conducting substrate that links the drain and the source with flowing electrons during a range of operations. Source and drain may be either P-type or N-type material.
These stresses, in addition to other MOS or layout parameters, can affect leakage current (Ioff) and drive current (Ion). Leakage current is current that flows across a dielectric area between two nearby conductors while a gate is off. Drive current is the current that flows to a drain of a gate or transistor when the gate is turned on. As can be appreciated, reducing geometries of layers such as silicon dioxide can increase leakage current due to dielectric effects. Consequently, absent due care to handle shrinking geometries, leakage current can grow to unmanageable levels causing excess standby power dissipation and reliability issues.
An accurate accounting of varying stresses along a gate's length can provide a more accurate determination whether the gate can function using the gate's current or proposed geometry coupled with other MOS or layout parameters.